The invention relates to an arrangement and a method for testing integrated circuits.
Integrated circuits are tested after being produced; they are generally fed for this purpose what are termed test vectors, which are data words that are fed to the inputs of the integrated circuit, and which produce at the outputs a specific response of the integrated circuit which is compared with a desired response. It can be established thereby whether the integrated circuit is working acceptably, that is to say has been correctly produced.
Owing to the increasing integration density of such integrated circuits, the number of necessary test vectors is increasing more and more. In accordance with the prior art, these test vectors are stored in vector memories. In this context there maybe several million test vectors per pin of the integrated circuit to be tested. This high number leads to a very high outlay for such test systems, and this leads, in turn, to an increase in production costs of the integrated circuit to be tested.
Another solution known in the prior art is what is termed a built-in self test (BIST), in the case of which there is provided on the integrated circuit a special test circuit which cooperates with an external, simple test system. This, in turn, has the disadvantage that an additional need for surface area arises for the test circuit on the integrated circuit, and that, furthermore, the useful circuit present on the integrated circuit must be modified. This in turn involves the risk that this useful circuit cannot be optimally designed.
It is an object of the invention to specify an arrangement and a method for testing integrated circuits which do not require any special measures on an integrated circuit to be tested, and which are relatively simple in their design.
This object is achieved according to the invention by means of the features of patent claim 1:
An arrangement for testing an integrated circuit, having a data word generator, which supplies deterministic data words, having means for test pattern generation, which modify the deterministic data words such that prescribed test patterns which can be fed to inputs of an integrated circuit to be tested, are produced, and having comparison means for comparing test output patterns of the integrated circuit with desired output patterns, the arrangement being provided outside the integrated circuit to be tested.
A voluminous vector memory can be eliminated in the case of the arrangement according to the invention for testing an integrated circuit. Instead of this, a data word generator which supplies deterministic data words is provided. This means that the data word generator supplies a sequence of data words which are known, that is to say can be predicted.
These deterministic data words of the data word generator are modified in a bitwise fashion with the aid of means for test pattern generation. In this case, the individual bits of each of these deterministic data words are modified such that prescribed, deterministic data patterns are produced. These test patterns are provided for the purpose of being fed to the inputs of the integrated circuit to be tested, and/of representing the desired output pattern.
Desired output patterns are likewise generated by the modification. The output signals of the integrated circuit to be tested, which are produced by the test patterns, are compared with these desired output patterns with the aid of comparison means.
It is possible in this relatively simple way to perform a test pattern generation which does not require a test pattern memory in which all the test patterns and/or vectors are stored. However, it is rather possible to use the data word generator and the means of test pattern generation to generate sequentially a sequence of consecutive test patterns without the need for these to be individually present in a memory.
The arrangement is provided outside an integrated and does not require on the integrated circuit that is to be tested any special measures, that is to say, in particular, no modification of the circuitry to be tested on the circuit, and also no additional surface area requirement on the integrated circuit.
The arrangement according to the invention will generally cooperate with a simple test system which essentially undertakes to control the arrangement and, if appropriate, evaluate the comparison results.
In accordance with a refinement of the invention, according to claim 2 a feedback shift register is provided as data word generator. Such a feedback shift register supplies pseudo random data words which are, however, generated according to a fixed pattern and are therefore known, that is to say are deterministic. Consequently, it is possible in this way, which is very simple in terms of circuitry, to generate the deterministic data words for the means for test pattern generation.
In accordance with a further refinement of the invention as claimed in claim 3, the means for test pattern generation are advantageously divided into bit flipping controller and bit flipping logic circuits which are driven by the bit flipping controller. The bit flipping logic circuits are provided for the purpose of individually modifying the bits of each deterministic data word supplied by the data word generator such that the desired value is achieved on the output side for the respective bit, such that the bit flipping logic circuits as a whole supply on the output side a desired prescribed deterministic test pattern data word which is fed to the inputs of the integrated circuit to be tested.
In the integrated circuit, it is possible to provide, if appropriate, circuit elements which have an undefined or memory response. No evaluation of the output patterns of the integrated circuit is possible during testing in this case. Generally, what is involved in this case is specific output test patterns in specific testing phases which cannot, or should not, be evaluated. In order to solve this problems, in accordance with a further refinement of the invention as claimed in claim 4, a masking logic circuit is provided which controls the comparison means in the arrangement such that only prescribed test output patterns of the integrated circuit to be tested are compared with the desired patterns. In other words, this logic masks specific output patterns, this is to say output patterns which are not to be evaluated for the reasons explained above are suppressed with reference to the evaluation.
A further refinement of the invention as claimed in claim 5 includes a test pattern counter which counts a clock signal which controls the test operation and relays the corresponding counting result to elements of the arrangement, in particular to the bit flipping controller and/or the masking logic circuit. Since, on the basis of the design of the arrangement according to the invention, a clock signal suffices for generating the test patterns, it is quite easily possible in this way to establish, on the basis of the counting result of the counter, the test phase in which a test operation is located.
The comparison means possibly need not compare each individual data word per se with a desired pattern; this can also be done, as provided in accordance with a further refinement of the invention as claimed in claim 6, by means of a signature register. The signature register combines each new output data word of the integrated circuit to be tested with a previous memory result by exclusive-OR logic operation. This operation is repeated with each new test pattern. At the end of the test operation, the value of the signature register is read out and compared with a desired value.
As provided in accordance with a further refinement of the invention as claimed in claim 7, the arrangement according to the invention can be implemented as a programmable logic circuit. As provided in accordance with claim 7, it can also advantageously be provided outside the integrated circuit as a link to a simple test system. In this case, the test system controls the arrangement according to the invention and supplies the required clock signals, for example.
The above-named object is achieved by a method for testing integrated circuits by means of the features of claim 10.